1. Field of the Invention
The present invention generally relates to transmission apparatuses, and more particularly to a transmission apparatus having a main signal processing device, a monitor control part and an intermediating part.
2. Description of the Related Art
FIG. 1 is a diagram showing a structure of a general optical transmission apparatus. An optical transmission apparatus 1 shown in FIG. 1 has a main signal processing part 2 and a monitor control part 3. The main signal processing part 2 has a main signal processing device 4 and an intermediating circuit part 5. The monitor control part 3 has a normal operation part 6 and a debug part 7.
The main signal processing device 4 terminals an optical input signal that is input from an optical fiber 8, and monitors the overhead such as the SOH (Section OverHead) and the LOH (Lime OverHead) of the optical signal such as the SONET and the SDH. In addition, the main signal processing device 4 carries out a cross-connect, add, drop or the like with respect to the optical signal depending on the functions available on the optical transmission apparatus 1, and further amplifies the optical signal, so as to output the amplified optical signal to an optical fiber 9.
The intermediating circuit part 5 converts a logical address supplied from the monitor control part 3 into a physical address of the main signal processing device 4, and holds set data supplied from the monitor control part 3 and writes the set data to the main signal processing device 4. The intermediating circuit part 5 also periodically reads and holds state data from the main signal processing device 4, and supplies the state data to the monitor control part 3.
The address conversion is made in the intermediating circuit part 5 because, while the physical address differ depending on the product model number or type of the main signal processing device 4, the functions of the monitor control part 3 are constant regardless of the product model number or type of the main signal processing device 4.
The normal operation part 6 of the monitor control part 3 sets to various parts of the main signal processing device 4 set data supplied from a host unit. In addition, the normal operation part 6 periodically reads and notifies the state of the main signal processing device 4 to the host unit.
A debugging terminal 10 is connected to the debug part 7, so as to debug the programs and the settings of the set data in the various parts of the main signal processing device 4.
FIG. 2 is a system block diagram showing an example of a conventional optical transmission apparatus. In FIG. 2, those parts that are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 2, the set data and logical address from the monitor control part 3 are irregularly written to and held in a write memory 12 within the intermediating circuit part 5 via an external bus 11.
The set data and write logical address are read from the write memory 12 at a periodic write timing determined by a timer part 13, and supplied to an interface part 14. The write logical address is converted into the physical address of the main signal processing device 4 by an address converting part 15 within the interface part 14. The set data and the physical address are supplied to the main signal processing device 4 via an internal bus 16, and the set data is written in a region of a write register 22 specified by the physical address via an interface part 21 within the main signal processing device 4. For example, the set data may be cross-connect information, band information or the like.
In addition, a read part 17 within the interface part 14 generates a read logical address at a periodic read timing determined by the timer part 13, and supplies the read logical address to the address converting part 15. The read logical address is converted into a physical address of the main signal processing device 4 by the address converting part 15, and is thereafter supplied to the main signal processing device 4 via the internal bus 16. Hence, the state data is read from a region of a read register 23 specified by the physical address. For example, the state data includes monitor information obtained from the overhead such as the SOH (Section OverHead) and the LOH (Lime OverHead), operation state information related to an operating state of the main signal processing device 4, and the like.
The read state data are supplied from the interface part 21 to the read part 17 within the interface part 14, and are written in a read memory 18 by the read part 17. The state data held in the read memory 18 are irregularly read from the monitor control part 3.
FIG. 3 is a timing chart for explaining a state data read operation and a set data write operation of the conventional optical transmission apparatus 1. The timer part 13 generates a timing signal shown in FIG. 3(A) at a constant period of 100 milliseconds, for example. Hence, the read part 17 makes a read access to the read register 23 at timings indicated by “R” in FIG. 3(B). In addition, the set data from the write memory 12 is written by a write access to the write register 22 at timings immediately after the read access, as indicated by “W” in FIG. 3(B).
The normal operation part 6 of the monitor control part 3 reads the state data from the read memory 18 for every 1 second, for example, as shown in FIG. 3(C), asynchronously to the timing signal shown in FIG. 3(A). In addition, the normal operation part 6 writes the set data and the write logical address to the write memory 12 if necessary.
A Japanese Laid-Open Patent Application No. 4-52891 proposes an IC memory card having card interface functions of the direct access system and the indirect access systems.
A Japanese Laid-Open Patent Application No. 2005-327078 proposes making a software access to a register within an LSI for simultaneously setting a plurality of registers, so as to simultaneously set initial values to the plurality of registers within the LSI.
Recently, the circuit scale of the main signal processing device 4 has become large, and the capacities of the write register 22 for setting and the read register 23 for monitor control have also become extremely large. As a result, the circuit scale and the power consumption will increase considerably if all of the monitor control information is to be sent to the monitor control part 3. For this reason, the intermediating circuit part 5 is provided with an address converting function so that the access is only made with respect to the minimum required addresses that are required for the operation of the optical transmission apparatus 1.
However, if an unimaginable problem that is outside the design range occurs at an evaluating stage where the actual main signal processing device 4 of the optical transmission apparatus 1 that is being developed is evaluated, there was a problem in that it is difficult to debug the main signal processing device 4 because the range in which the read access can be made to the read register 23 from the intermediating circuit part 5 is restricted, and there exist within the main signal processing device 4 regions that cannot be read from the intermediating circuit part 5.